This invention relates to an event based semiconductor test system for testing semiconductor devices, and more particularly, to an event based test system having means for generating multiple end of test signals each indicating an end of test in a corresponding pin unit or a pin-unit group where two or more pin-unit groups in the test system perform test operations independently from one another.
In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals or test patterns produced by a semiconductor test system at its appropriate pins at predetermined test timings. The semiconductor test system receives output signals from the IC device under test (DUT) in response to the test signals. The output signals are sampled by strobe signals with predetermined timings to be compared with expected data to determine whether the DUT functions correctly or not.
Traditionally, timings of the test signals and strobe signals are defined relative to a tester rate or a tester cycle of the semiconductor test system. Further, waveforms and vectors of the test signals are also defined with respect to each tester cycle. Such a test system is sometimes called a cycle based test system. In a cycle based test system, various different types of data are necessary and thus data processing therein tends to be complicated. Thus, it is considered that a cycle based test system is difficult to achieve a per-pin architecture where hardware and software for each tester pin is independent from one another.
FIG. 1 is a schematic diagram showing an example of such a cycle based test system. In FIG. 1, a sequence controller 12 is a tester processor provided within the semiconductor test system for controlling the operation of the test system. Based on address data from the sequence controller 12, a pattern memory 14 produces pattern data and waveform data relative to each tester cycle. The pattern data and waveform data are provided to a pin data formatter 17 through a pin data selector 16. Based on the address data from the sequence controller 12, a timing memory 13 generates timing data which typically specifies delay times relative to the start of each tester cycle. The timing data is also provided to the pin data formatter 17.
A test signal is produced by the pin data formatter 17 with use of the pattern data and waveform data from the pattern memory 14 and the timing data from the timing memory 13. A pin driver/comparator 18 applies the test signal to a device under test (DUT) 19 with a specified amplitude and slew rate. The pin data selector 16 selectively transfers the pattern data and waveform data for corresponding tester pins to the pin data formatter 17. In other words, the pin data formatter 17 is configured by a plurality of data formatters with one-to-one correspondence with the tester pins (test channels). Similarly, the pin driver/comparator 18 as also configured by a large number of drivers and comparators corresponding to the tester pins.
The pin driver/comparator 18 receives a response signal from the DUT 19 resulted from the test signal. in the driver/comparator 18, the response signal is converted to a logic signal by an analog comparator with reference to predetermined threshold voltages by the timings of strobe signals, and the resultant logic signal is compared with expected value data by a logic Comparator. The result of the logic comparison indicates pass/fail of the DUT which is stored in a failure memory 15 corresponding to the address of the DUT 19. The test results stored in the failure memory 15 is used in a failure analysis stage after the test.
In the cycle based test system noted above, all of the tester pins (DUT pins) share the same memory areas in the pattern memory 14 and timing memory 13 that store the pattern data and timing data. In other words, each tester pin cannot operate independently from one another. This common sharing of storage space requires the test program to be executed from beginning to the end for all tester pins. Thus, the cycle based test system inherently requires only one end-of-test indication, i.e., an end-of-test (EOT) signal generation mechanism.
In testing complicated recent semiconductor devices by such a conventional test system, there arises a problem that a test time increases when the device under test includes two or more different functional blocks. For example, a system-on-chip (SOC) IC device has a plurality of functional blocks or cores therein to perform an intended overall function. A typical SOC device requires multiple clock frequencies for the functional blocks (cores or modules) that compose the SOC device. Sometimes, these clock frequencies do not share any common harmonics and are therefore asynchronous with one another.
An example of SOC device is shown in FIG. 2 which is a typical multimedia SOC. The SOC 19 has several functional blocks or functional cores including a PLL (phase lock loop) 22, a TV encoder 23, a memory controller 24, a display controller 25, a PCI module 26, a RISC 27, and an MPEG engine 28. In FIG. 2, each functional core shows the clock frequency which is asynchronous with one another.
Since each functional core in this example operates under different clock frequencies, each of the functional cores has to be tested separately. In this cycle based tent system, however, since the test signals and strobes are generated based on the data from the same pattern memory and timing memory, it is not possible to generate test signals asynchronous to one another. In other words, the conventional cycle based test system cannot conduct different types of test in a parallel fashion at the same time. Since each functional core has to be tested one by one in a series fashion, the total testing time is the sum of all functional cores"" test times.
FIG. 3 shows an example of process for testing the SOC 19 of FIG. 2. As noted above, each functional core is tested one by one in a series fashion from a test start t0 to a test end te. The test system tests the PCI block which starts at t0 and ends at t1, then tests the RISC block which starts at t1 and ends t2, and so on. This results in that while one of the functional cores is tested (solid line in FIG. 3), all the other cores are in idle (dotted line in FIG. 3). Therefore, it takes a very long time to complete the test of the SOC device of FIG. 2.
Therefore, it is an object of the present invention to provide an event based semiconductor test system which is able to perform a plurality of different tests in a parallel fashion at the same time.
It is another object of the present invention to provide an event based semiconductor test system which is able to perform a plurality of different tests in a parallel fashion at the same time by incorporating means for generating multiple end of test signals.
It is a further object of the present invention to provide an event based semiconductor test system which is capable of generating multiple signals each indicating an end of test in a pin-unit group where each pin-unit group conducts test operations independently from one another.
The present invention is an event based test system for testing an electronics device under test (DUT) by producing events of various timings for supplying test signals to the DUT and evaluating an output of the DUT at the timings of strobe signals. The event based test system is freely configured by a plurality of groups of tester pins or pin units where each group is able to perform test operations independently from the other. The start and end timings of the test in each group are independently made by means of generating multiple end of test signals.
In the present invention, the event test system includes a plurality of pin units to be assigned to pins of a semiconductor device under test (DUT) for testing the DUT where each of the pin units operates independently from one another, and each of the pin units has an event memory for storing event timing data for producing test signals to be applied to the corresponding pin of the DUT, and an event controller for controlling an overall operation of the pin unit by generating the test signals based on the event timing data from the event memory and evaluating a response output of the DUT.
The event based test system further includes means for generating an end of test signal for indicating an end of current test that has been performed by a corresponding pin unit where the end of test signal is generated for each pin unit independently from other pin units, and a system controller for controlling an overall operation in the event based test system by communicating with the event controller in each pin unit and providing the event timing data to the event memory in each pin unit. The end of test signal for each pin unit is selected by condition specified by the system controller and the selected end of test signal is provided to the system controller and to the other pin units.
According to the present invention, the event based semiconductor test system is capable of producing the events of test signals with various timings based on the event data stored in the event memory to evaluate the semiconductor device. The event based test system includes a plurality of pin units each of which is capable of producing a test signal for a specified pin of the DUT and means for generating an end of test signal with respect to each pin unit independently from the other pin units.
Therefore, the event based test system is capable of performing a plurality of different tests in a parallel fashion at the same time. Further, the event based test system can freely assign a plurality of pin units to several pin-unit groups and generate multiple signals each indicating an end of test in a corresponding pin-unit group where each pin-unit group carries out test operations independently from one another. Thus, the event based test system can perform a plurality of different tests in parallel at the same time.